"Understand RTL first, use HLS second."
Phase detection in digital PLLs, or mixing in SDR receivers. Part 4: The High-Level Synthesis (HLS) Revolution A significant portion of the updated Primer addresses Vivado HLS (now part of Vitis). Traditional RTL design (Verilog/VHDL) is precise but slow to iterate. HLS allows you to write C/C++ and compile it to RTL. Xilinx University Program - DSP for FPGA Primer...
It teaches you to think in "dataflow." Instead of writing a loop to compute 100 multiplications, you design 100 physical multipliers. 2.2 Fixed-Point Arithmetic Most engineering students despise fixed-point arithmetic. Floating-point is intuitive; fixed-point requires scaling, quantization analysis, and overflow management. Yet, FPGAs excel at fixed-point. Floating-point units consume massive logic resources; fixed-point DSP48 blocks run at 500+ MHz. "Understand RTL first, use HLS second
Visit the AMD XUP Academic website today. Download the DSP for FPGA materials. Flash your first bitstream. The world of real-time digital signal processing awaits. HLS allows you to write C/C++ and compile it to RTL
The is your key. It transforms a student who knows the Fourier Transform into an engineer who can implement a real-time 16-tap filter running at 500 MHz on an Artix-7.